Modeling SPIRIT IP-XACT with UML MARTE

Large System-on-Chips (SOC) are now built by assembly of existing components, modeled at different representation levels(TLM, RTL . . . ). The IP-XACT standard was recently developed to help normalize interfaces of IP components, and ease their composition. Currently it does not fully face timing representation issues. The equally recent MARTE UML profile focuses explicitly on the rich expression of time (physical or logical), clocks, and timing features. We attempt here to embed SPIRIT IP-XACT representations as MARTE models. This leaves open the possibility to extend the formalism with timing aspects, while it provides graphical editing functionalities and a way to experiment